Semiconductor wafer array with electrically conductive compliant material

ABSTRACT

A semiconductor wafer array comprising a plurality of wafers of semiconductor material. Each of the wafers is provided with cone-shaped or pyramid-shaped vias. Inserted in each of the vias is a correspondingly shaped wad of electrically conductive compliant material for forming continuous vertical electrical connections between the wafers in the stack. The base of each wad makes connection to a bonding pad on the surface of a lower wafer as well as to the electrically conductive compliant material in the lower wafer.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a continuation-in-part of application Ser.No. 06/887,129, filed July 17, 1986, now U.S. Pat. No. 4,897,708, issuedJan. 30, 1990, entitled "Semiconductor Wafer Array" and assigned to theassignee of the present application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor wafer arrays in generaland in particular to a method and apparatus comprising a stacked arrayof semiconductor wafers which are vertically interconnected by means ofa plurality of wads of an electrically conductive compliant material.

2. Description of the Prior Art

Since the development of integrated circuit technology, computers andcomputer storage devices have been made from wafers of semiconductormaterial comprising a plurality of integrated transistor circuits. Afterthe wafer is made, the circuits are separated from each other by cuttingthe wafer into small chips. Thereafter, the chips are bonded to carriersof varying types, interconnected by tiny wires and packaged.

The above-described process of making computers and computer memorydevices has been found to be time-consuming and costly and the use oftiny wires to electrically connect the chips has often been found to beunreliable. Moreover, the length of the wires which has been required tomake the necessary interconnections between chips has been found toresult in undesirable signal delays as the frequency of operation of thedevices has increased.

To avoid some of the disadvantages of the prior technology, a number ofefforts have been made to eliminate the need for separating chips in awafer and interconnecting them using wires. For example, a technologycalled Wafer Scale Integration (WSI) attempted to do this. In WSI,techniques were used to wire together all the chips on a single wafer;however, the attempts thus far have not been successful. It was foundthat the line widths required to provide a computer on a single wafer,even when multiple layers of lateral connections were used, became sosmall that it was not possible to obtain lines of sufficient length andprecision to make the necessary interconnections between the circuitstherein.

The use of WSI technology which uses lateral connections to connect thecircuits on a single wafer also has disadvantages when used for makingstorage devices. In practice, all wafers comprise randomly locateddefects. The defects render the circuits affected unusable. Since WSItechnology incorporates the defective circuits at the time a wafer ismade, it is difficult and costly to build in an amount of redundancysufficient to overcome the effect of the defects. In any event, even ifa single wafer comprising a large number of storage cells could be builtat a reasonable cost, the memory capacity required in many applicationsfar exceeds that which can be provided on a single wafer. Therefore,such applications would still require that a plurality of such wafers beused and that the wafers be interconnected in some suitable manner.

Other attempts to avoid the disadvantages of interconnecting a pluralityof stacked wafers using wires have involved large scale parallel arrayprocessors and memory devices in which parallel circuit members areinterconnected using vertical columns of solid, dense conductivematerial such as solder, copper, etc. For example, in U.S. Pat. No.4,368,106, there is disclosed a process for making a solid, densemetallic feedthrough in a semiconductive material comprising the use ofan electroforming solution and apparatus. In U.S. Pat. No. 4,394,712,there is disclosed a process for making a feedthrough in a semiconductorwafer array comprising three solid concentric materials including acentral core of solder. In making the array, a plurality of the wafersare stacked and solder, which has been implanted in vias in the wafersand slightly beyond, is caused to flow, interconnecting the wafers.

The use of solid, dense feedthroughs to interconnect a plurality ofwafers is typically costly and time consuming and makes it difficult toseparate the wafers in the event that a wafer is or becomes defectiveand requires repair or replacement. The reason for this is that the heatrequired to form and/or sever the interconnections can be damaging tothe wafers and the circuits located therein. Also, differential thermalcoefficients of expansion between the rigid feedthroughs and thesurrounding semiconductor and other materials can result in damagingstresses during thermal cycling.

In applicant's above-described co-pending patent application there isdisclosed a semiconductor wafer array. In the array each wafer isprovided with one or more vias, as by chemical or laser drilling or thelike. After the walls of the vias and the wafers are coated with a layerof electrically insulating material, the wafers are stacked one on topof another with the vias in one wafer placed in registration withcorresponding vias in adjacent wafers and clamped or bonded together asby an adhesive. After the wafers are bonded to a larger diameterinterconnection wafer, all of the vias in the array are filled with anelectrically conductive liquid. After the vias are filled, the exposedends of the vias are sealed with compliant material. The array is thenpackaged with electrical connections made thereto by means of wiresconnecting pads on the interconnection wafer and externally projectingpin members.

While avoiding the disadvantages associated with rigid verticalelectrical feedthroughs, the use of electrically conductive liquid toform the interconnections does require special tooling to fill the vias.

In applications requiring fewer vertical feedthroughs which thus lessenthe need for very small vias and the use of an electrically conductiveliquid to form the vertical electrical connections, it is found thatvias which are somewhat larger may be filled with an electricallyconductive compliant material. Such material may, for example, comprisewads of very fine wire or wads of electrically conductive elastomericmaterial.

The idea of using compliant wadded fine wire, sometimes called "fuzzwire", to make an electrical connection between two electricalconductors is old, dating back to the use of "fuzz wire" to make RFseals in microwave cabinets and waveguides. The idea of using compliant"fuzz wire" for providing vertical connections between individual boardsin a stack of printed circuit boards is also known and was proposed inU.S. Pat. Nos. 4,574,331 and 4,581,679 by Robert Smolley.

In his patents Smolley discloses a stack of printed circuit boards. Oneach of the boards there is provided an electrical contact area or pad.The pad may be formed on the surface of the boards or on a metallicfeedthrough inserted in a via in the boards. Interposed between each ofthe boards there is an insulated board referred to as a button board.The button board has a plurality of circular openings formed through it,and in each opening is placed a connector element, also known as a "fuzzbutton" or button connector. The button connector is formed from asingle strand of metal wire, each strand being wadded together to form anearly cylindrical "button" of material. When the button elements areplaced in the holes, the button material projects slightly out of theholes on both ends. When a compressive force is applied to the stack ofprinted circuit boards, the insulated board interposed therebetween andthe button elements, the latter are compressed against the contact areasor pads forming an electrical connection therebetween.

For several reasons, the use of "fuzz wire" in the manner disclosed bySmolley to form vertical electrical connections between a stack ofprinted circuit boards has certain disadvantages. For example, toprovide vertical electrical connections between a stack of printedcircuit boards, metallic feedthroughs are required to be inserted invias provided in the boards and an insulated board is required toinsulate the printed circuit boards from each other and to hold thebutton elements in place. Because of the cylindrical shape of the buttonelements, both the metallic feed throughs and the insulated boards arerequired to make an electrical connection to circuits on the boards andto insure the application of uniform compressive forces to the buttonelements. These features, the insulated boards and the metalicfeedthroughs, require a considerable amount of space and increase thecomplexity of the manufacturing and assembly process.

In U.S. Pat. No. 4,029,375 issued to Henry Gabrielian, there isdisclosed in two embodiments of an electrical connector the use of acylindrically shaped metalic helical spring member for verticallyelectrically interconnecting electrical pads located on two spaced-apartprinted circuit boards. As in the case of the Smolley invention,however, Gabrielian also requires an intermediate insulating board toboth insulate the printed circuit boards from each other and to hold thespring members in position in order to make the necessary electricalconnections. The use of an intermediate insulating board to insulate theprinted circuit boards from each other and to hold the electricallyconnecting spring members adds expense to the apparatus, increases theoverall size of the apparatus, as well as adding steps to thefabrication of an array using them.

SUMMARY OF THE INVENTION

In view of the foregoing, principal objects of the present invention area method and apparatus comprising a semiconductor wafer array in whichthe individual wafers in the array, as distinguished from printedcircuit boards, are stacked one on top of another and verticallyelectrically interconnected using an electrically conductive compliantmaterial such as a wad of fine wire or a wad of electrically conductiveelastomer.

In accordance with the above objects, each wafer in the array isprovided with one or more vias, as by chemical or laser drilling or thelike. After the walls of the vias in the wafers are coated with a layerof electrically insulating material, the vias are filled with wads ofelectrically conductive compliant material and the wafers are stackedone on top of another.

The shape of the vias and the wads are important features of the presentinvention. In order to eliminate the necessity for a separate means forholding the individual wads of electrically conductive compliantmaterial in position and to provide vertical electrical connectionsbetween wafers as well as lateral electrical connections to electricalcircuits on each of the wafers, the vias and wads are formed withinwardly sloping walls having an overall cone, hourglass or pyramidshape. A ring-shaped electrical pad which is electrically laterallyconnected to circuits on a wafer is provided surrounding the apex orsmall end of the vias as needed. The apex or small end of the wads isformed to project beyond the apex of the vias and the "base or largeend" of the wads is formed to project beyond the base of the vias. Whena stack of such wafers is formed the apex of a wad is compressed intothe base of a wad in a wafer adjacent thereto. At the same time the baseof the latter wad is compressed against the electrically conductivering-shaped pad thus forming both a vertical electrical connection to anoverlying wafer as well as to the electrical circuits connected to thepad.

In the process of fabricating an array, the wafers are oriented with theapex of cone-shaped or similarly shaped vias facing downwardly.Cone-shaped or similarly shaped wads of electrically conductivecompliant material are then placed in the vias. Because of theirrespective shapes, the wads are prevented from falling out of the viasso long as the wafers are not turned over. After all of the vias in thewafers are loaded with the wads, the wafers are stacked together andplaced on a base plate.

The base plate is fitted with a plurality of electrical feedthrough pinswhich make contact with the base of the wads of electrically conductivecompliant material in the lowest one of the wafers in the array. Thewafer at the top of the stack is provided with a pressure applyingmember so as to press all of the wafers together, thereby compressingthe individual wads of electrically conductive compliant materialtogether as described above. As will be appreciated wafers may be addedto or removed from the stack as required and the over-all change in thesize of the stack merely corresponds to the thickness of the waferinvolved.

BRIEF DESCRIPTION OF THE DRAWING

The above and other objects, features and advantages of the presentinvention will become apparent from the following detailed descriptionof the accompanying drawing, in which:

FIG. 1 is a cross-sectional view of a semiconductor wafer arraycomprising a plurality of stacked wafers according to the presentinvention;

FIG. 2 is a plan view of one of the wafers of FIG. 1 showing severalring-shaped electrical pads on one surface thereof;

FIG. 3 is a cross-sectional view taken in the direction of lines 3--3 ofFIG. 2;

FIG. 4 is a cross-sectional view showing the wafer of FIG. 3 after ithas been coated with an etch-resistant material;

FIG. 5 is a cross-sectional view of the wafer of FIG. 4 after it hasbeen patterned to expose a square area on the backside of thesemiconductor wafer substrate beneath the pads;

FIG. 6 is a cross-sectional view of the wafer of FIG. 5 showing twothrough-holes provided therein;

FIG. 7 is an enlarged cross-sectional view of one of the vias shown inFIG. 6 after the etch-resistant coating shown in FIGS. 4-6 is removedfrom the center of the ring-shaped pad surrounding the via.

FIG. 8 is a cross-sectional view of the via of FIG. 7 after the sharpedges at the apex of the via are removed;

FIG. 9 is a cross-sectional view of the via of FIG. 8 after its wallshave been coated with an electrically insulating layer.

FIG. 10 is a cross-sectional view of the via of FIG. 9 after theetch-resistant coating shown in FIGS. 4-9 is removed from thering-shaped pad.

FIG. 11 is a cross-sectional view of the via of FIG. 10 after a wad ofcompliant electrically conductive fine wire is inserted therein;

FIG. 12 is an enlarged partial cross-sectional view showing two wafersstacked one on top of another between a dummy wafer and a base platewith the wad of FIG. 11 inserted in each of the vias located thereinaccording to the present invention;

FIG. 13 is an enlarged partial cross-sectional view showing analternative embodiment of the present invention, comprising electricallyconductive compliant elastomeric material;

FIG. 14 is an alternative embodiment of the present invention showingthe top of a wad of fine wire compressed onto the pad surrounding thevia; and

FIG. 15 is a partial cross-sectional view showing relative dimensions ofthe vias in the wafers.

DETAILED DESCRIPTION OF THE DRAWINGS

Referring to FIG. 1, there is provided in accordance with the presentinvention a semiconductor wafer array designated generally as 1. In thearray 1 there is provided a housing 2 mounted on a base plate 3. In thehousing 2 there is provided a plurality of side walls 4, 5 and 6 and atop wall 7. A front wall corresponding to side walls 4-6 is not shown.Located in the housing 2 between the base plate 3 and top wall 7, thereis provided a stack of semiconductor wafers 10-18. In the stack ofwafers 10-18, the bottom wafer 10 is located adjacent to the base plate3. The top wafers 18 is located nearest to the top wall 7. Wafer 18 maybe a dummy wafer which is used simply for terminating the verticalelectrical connecting members and forming an electrical connection withthe pads on wafer 17 as will be further described below. On top of wafer18 between wafer 18 and top wall 17, there is provided a compliantelectrically insulating thermally conductive pad 20. Pad 20 is locatedbetween the wafer 18 and the top wall 7 to compensate for thermalexpansion and contraction of the stack of wafers 10-18 and forconducting heat from the stack of wafers 10-18 to the top wall 7.Extending from the top wall 7 there is provided a plurality of metallicfingers 21. Fingers 21 comprise cooling fins for dissipating heat fromthe housing 2.

Extending through the base plate 3 there is provided a plurality ofelectrical pin members 22. Pin members 22 are provided for makingelectrical contact with electrically conductive compliant material invias in the stack of wafers 10-18, as will be further described below.

In practice, the base plate 3 comprises insulating material, such asceramic material, for insulating the pin members 22 from each other, andthe side wall members 2 and 4 may comprise a metallic material. The freearea within the housing 2 may be filled with a conventional electricallynon-conductive gaseous or liquid material to facilitate the dissipationof heat from the housing 2.

In each of the wafers 10-17 there is provided a plurality ofhourglass-shaped vias 25. Corresponding pyramid-shaped recesses 26 arenormally provided in dummy wafer 18. In each of the vias 25 and recesses26 there is provided a wad 27 of an electrically conductive compliantmaterial, such as, for example, a fine wire or an electricallyconductive elastomer. The vias 25 and recesses 26 in the wafers 10-18are placed in registration with a corresponding via in an adjacentwafer, such that the wads 27 of electrically conductive compliantmaterial in the vias combine to form a conductive vertical columnproviding electrical connections from feedthrough pins 22 to each ofsaid semiconductor wafers 10-18.

While the embodiment of FIG. 1 shows a sealed housing 2, it isunderstood that conventional ports for circulating cooling gases orfluids may be added to the housing 2 in a manner as best fits the heatflow requirements of the application circuits located therein. Also, incertain applications, certain of the vias 25 may provide verticalconnections between two or more but less than all of the wafers.

Referring to FIGS. 2-11, the steps used for fabricating each of thesemiconductive wafers in the stack of wafers 10-18 will now bedescribed. For convenience, the description will be made with respect towafer 10, it being understood that the other wafers 11-17, except forpossible differences in the electrical circuits provided therein, aresubstantially identical insofar as the present invention is concerned.

Referring to FIGS. 2 and 3, wafer 10, a 1,0,0 silicon wafer, is providedwith a first or topside surface 30 and a second or backside surface 31.Electrical circuits, e.g. logic circuits, memory cells, or the like (notshown), are provided in the surface 30 and laterally electricallyconnected to one or more ring-shaped pads 32-37. While only 6 pads areshown, it is to be understood that many such pads are normally presenton each wafer.

The surfaces 30 and 31 of the wafer 10 are then provided with a coating34 of etch-resistant material such as silicon nitride as shown in FIG.4. After the wafer 10 has been coated with the etch-resistant material,the coating 34 is patterned on the backside 31 of the wafer 10 bytechniques known in the microlithographic art and plasma-etched so as toprovide square openings 35 in the nitride coating exposing the wafer 10beneath the pads 32-37 as shown in FIG. 5. After the square openings 35are produced, the wafer 10 is subjected to a conventional anisotropicetch process, such as 85° C. KOH at 35% concentration, that produces atruncated pyramid-shaped hole or recess 36 in the wafer 10 as shown inFIG. 6. Other techniques may also be used for fabricating the holes 36such as those comprising laser means and combined laser and etch means.Any means that yields roughly pyramid-, cone- or hourglass-shaped vias,while avoiding damage to the surface of the wafer, may be used for thepurpose of this invention.

Referring to FIG. 7, there is shown an enlarged cross-sectional view ofthe pad 33 and hole 36 in the wafer 10. As shown in FIG. 7, theanisotropic etch process used for making the holes 36 as described abovewith respect to FIG. 6 produces extremely sharp and therefore somewhatfragile edges 37 which are subject to chipping and cracking. In order toremove the sharp edges 37, the silicon nitride coating 34 in the centerof the pad 33 is removed and the wafer 10 subjected to a second shortanisotropic etching process. This etching process produces a secondinverted truncated pyramid-shaped hole 38, thus forming square-sidedhourglass-shaped vias 25 as shown in FIGS. 1 and 8.

After the vias 25 are formed in the wafer 10, an insulating layer 40 ofsilicon nitride is grown or deposited on the walls of the vias 25 so asto provide electrical isolation of the wafer 10 as shown in FIG. 9.Thereafter, the silicon nitride coating 34 is removed from the bondingpad 33 as shown in FIG. 10. For the purpose of this disclosure, it maybe assumed that the wafers 10-18 are approximately 0.020 inches (20mils) thick, that the aperture 41 at the top of the via 25 isapproximately 10 mils on a side and that the aperture 42 at the bottomof the via 25 is approximately 30 mils on a side.

Referring to FIG. 11, there is provided in each of the vias 25 a wad ofelectrically conductive compliant material 45. In one of the embodimentsof the present invention, the wad 45 comprises a wad of single strandfine wire. The shape of the wad 45 is roughly that of a pyramid or acone. The diameter of the wire used to make the wad 45 is approximately1/10th that of the width of the top side aperture 41, i.e. 1 mil, andthe volume of the wire used is such as to fill the vias 25 to within 10to 20% of their volume; the remainder of the via volume comprising theair space between the wire in the wad. Any suitable conventional meansmay be used for pre-forming the wads 45 into the desired shape.

Referring to FIG. 12, there is shown an assembly 50 comprising three ofthe wafers 10-18, namely wafers 10, 11 and 18, having vias 25 and 26,each containing a wad of compliant fine wire as described above withrespect to FIG. 11. The wafers 10, 11 and 18 are supported on the base 3with the vias 25 and 26 in each of the wafers located in registrationwith one of the feedthrough pins 22 in the base 3. Located on top of thestack of wafers 10, 11 and 18 there is also provided the thermallyconductive pad 20 described above with respect to FIG. 1. The wafers 10,11 and 18 may also contain through-holes for the purpose of receivingalignment pins (not shown) for holding the vias in the wafers inalignment. Of course, other means may also be used for keeping thewafers in alignment.

The configuration of the vias 25 and 26 and the wads 45 as shown inFIGS. 11 and 12 is an important feature of the present invention. Thepyramid or cone shape of each of the wads 45 allows its base or largerend to make connection to the wafer bonding pad 33 while its apex orsmaller end makes connection to the base of the next higher vertical wad45. In the case of the bottom wafer 10, the base of the wad 45 thereinmakes an electrical contact with the feedthrough pin 22, as also shownin FIG. 1. In the case of the top dummy wafer 18, the dummy wafer 18,without circuits, is used as a containment for the top level of wads 45so as to compress the wads and provide an electrical connection to thepad 33 on the topmost circuit wafer 11 and the underlying wad 45 in thewafer 11.

As an alternative to the fine wire wads 45 of FIG. 12, FIG. 13 shows ashaped form of conventional compliant conductive elastomer 51. Aplurality of wads 51 may be used in place of wads 45 if desired.

Referring to FIG. 14, there is provided in an alternative embodiment ofthe present invention a wad of electrically conductive compliant wirematerial 55. Wad 55 is substantially identical to wad 45 described abovewith respect to FIGS. 11 and 12 with the exception that the wad 55 ismade to extend through the wafer 10 and a portion 56 thereof is thencompressed back against the bonding ring pad 33 so as to cause the waferto retain the mass of fine wire 55 in the vias 25 and to insure contactto the bonding ring 33. This configuration may be used in place of thewads 45 used in wafer 10-17 and, if used in wafer 17 at the top of thestack, the use of the dummy wafer 18 to insure the making of anelectrical contact to the pad 33 on the wafer 17 may be avoided.

Referring to FIG. 15, the width s2 of the vias 25 is given by theequation

    s2=s1+√2 t-2√2 rt

where

s1 is the width of the apex of the vias 25,

t is the thickness of the wafer 10 and

r is a constant having a value less than unity, (e.g. 0.1-0.2.)

While several embodiments of the present invention are described above,it is contemplated that various modifications may be made theretowithout departing from the spirit and scope of the present invention.For example, the second etch described above for making the hole 38 maybe an isotropic etch thereby producing the same sized hole but withparallel sidewalls. Of course, the pads 45 may be similarly shaped. Inall cases, the methods and means used for forming the vias and the wadscomprise conventional semiconductor wafer processing techniques.Accordingly, it is intended that the embodiments described be consideredonly as illustrative of the present invention and that the scope thereofshould not be limited thereto but be determined by reference to theclaims hereinafter provided and their equivalents.

What is claimed is:
 1. A semiconductor wafer array comprising:aplurality of wafers of semiconductors material which are stacked one ontop of another, each of said plurality of wafers having(a) a via whichis in registration with a via in an adjacent wafer, said via in each ofsaid plurality of wafers having a first end terminated by a first holein a first surface of each of said wafers, a second end terminated by asecond and relatively larger hole in a second and opposite surface ofeach of said wafers, and an inwardly directed wall surface in at least aportion of the wall between said first and said second ends; (b) meansfor electrically insulating an exposed surface of said via in each ofsaid plurality of wafers between said first and said second ends; (c) anelectrically conductive pad surrounding said first hole of said via ineach of said plurality of wafers for making an electrical connection toelectrical circuits located on said first surface of each of saidplurality of wafers; and (d) an electrically conductive compliantmaterial which is located in said via in each of said plurality ofwafers which, when not compressed, extends outwardly beyond respectiveplanes of said first and said second holes of said via in each of saidplurality of wafers; and means for stacking a first one of saidplurality of wafers on top of a second one of said plurality of waferssuch that the compliant material which extends beyond said second holeof said via in said first one of said plurality of wafers will make anelectrical contact with said electrically conductive pad surroundingsaid first hole of said via in said second one of said plurality ofwafers and said compliant material which extends from said first hole ofsaid via in said second one of said plurality of wafers.
 2. An arrayaccording to claim 1 wherein said inwardly directed wall surface of saidvias in each of said wafers restricts movement of said compliantmaterial in said vias through said first hole when pressure is appliedto said compliant material in the direction of said first hole.
 3. Anarray according to claim 1 wherein said electrically conductivecompliant material comprises a cone-shaped portion.
 4. An arrayaccording to claim 3 wherein said electrically conductive compliantmaterial comprises an elongated portion having substantially parallelside portions which extend from the apex of said cone-shaped portion. 5.An array according to claim 1 wherein said via comprises side wallshaving the shape of a truncated pyramid.
 6. An array according to claim5 wherein said via comprises an elongated portion having substantiallyparallel side walls which extend from the truncated end of saidpyramid-shaped side walls.
 7. An array according to claim 3 wherein saidcompliant material comprises a wad of wire.
 8. An array according toclaim 3 wherein said compliant material comprises a compliantelectrically conductive elastomer.
 9. An array according to claim 1wherein said first surface of each wafer comprises a compliantelectrically insulating material.
 10. A semiconductor wafer arraycomprising:a housing having a base plate and a top wall; a plurality ofwafers of semiconductive material which are stacked one on top ofanother between said base plate and said top wall, one of said wafersbeing located adjacent to said base plate, another of said wafers beinglocated nearest to said top wall, each of said wafers having at leastone via which is in registration with a via in another of said wafers,said via in each wafer having a first end terminated by a first hole ina first surface of said wafer, a second end terminated by a second holein a second and opposite surface of said water, said second hole havinga larger diameter than said first hole and an inwardly directed wallsurface in at least a portion of the wall between said first and saidsecond ends of said via; means for electrically insulating the exposedsurface of said via between said first and second ends thereof; anelectrically conductive pad surrounding said first hole in each waferfor making an electrical connection to electrical circuits located onsaid first surface of said wafer; an electrically conductive compliantmaterial which is located in said via in a wafer and, when notcompressed, extends outwardly beyond the plane of said first and saidsecond holes of said via in each wafer so as to make an electricalcontact with the electrically conductive pad surrounding said hole andthe compliant material in the via of an underlying wafer; anelectrically conductive feedthrough pin mounted in said base plate formaking an electrical contact with said electrically compliant materialin said via in said wafer located adjacent to said base plate; and meanslocated between said top wall and said wafer located adjacent to saidtop wall for applying pressure to said stack of wafers such that saidcompliant material in a wafer is compressed against the compliantmaterial in a wafer adjacent thereto for forming an electricallyconductive path between said adjacent wafers.
 11. An array according toclaim 10 wherein said pressure applying means comprises means forconducting heat from said stack of wafers to said top wall.
 12. An arrayaccording to claim 11 wherein said heat conducting means for conductingheat from said stack of wafers to said top wall comprises a compliantmember for compensating for thermal expansion and contraction of saidstack of wafers.
 13. An array according to claim 12 comprising meansmounted in said top wall and extending outwardly therefrom fordissipating heat from said top wall.
 14. An array according to claim 10wherein each of said vias comprises side walls having the shape of atruncated pyramid.
 15. An array according to claim 14 wherein each ofsaid vias comprises an elongated portion having substantially parallelside walls which extend from a truncated end of said pyramid-shaped sidewalls.
 16. An array according to claim 10 wherein said compliantmaterial comprises a wad of wire having a bottom portion comprising aninclined surface extending inwardly from the bottom thereof toward thetop thereof and an upper portion with generally parallel side wallportions.
 17. An array according to claim 10 wherein said compliantmaterial comprises a wad of electrically conductive elastomer materialhaving a bottom portion comprising an inclined surface extendinginwardly from the bottom thereof toward the top thereof and an upperportion with parallel side wall portions.
 18. An array according toclaim 16 wherein said bottom portion is cone-shaped.
 19. An arrayaccording to claim 16 wherein said bottom portion is pyramid-shaped. 20.An array according to claim 17 wherein said bottom portion iscone-shaped.
 21. An array according to claim 17 wherein said bottomportion is pyramid-shaped.